DE2-70 User Manual
5.8 Using the 24-bit Audio CODEC
The DE2-70 board provides high-quality 24-bit audio via the Wolfson WM8731 audio CODEC
(enCOder/DECoder). This chip supports microphone-in, line-in, and line-out ports, with a sample
rate adjustable from 8 kHz to 96 kHz. The WM8731 is controlled by a serial I2C bus interface,
which is connected to pins on the Cyclone II FPGA. A schematic diagram of the audio circuitry is
shown in Figure 5.14, and the FPGA pin assignments are listed in Table 5.12. Detailed information
for using the WM8731 codec is available in its datasheet, which can be found on the manufacturer's
web site, or in the Datasheet/Audio CODEC folder on the DE2-70 System CD-ROM .
J11
LINE IN
C38
1u
R99
4.7K
PHONE JACK B
VCC33
VCC33
R108
R109
C39
1u
R101
4.7K
R100
R102
4.7K
4.7K
AGND
2K
2K
AGND
AGND
I2C_SDAT
J10
MIC IN
I2C_SCLK
R103
330
I2C ADDRESS READ IS 0x34
I2C ADDRESS WRITE IS 0x35
U13
C40
1u
PHONE JACK P
A_VCC33
AGND
1
2
3
4
5
6
7
XTI/MCLK
XTO
DCVDD
DGND
DBVDD
CLKOUT
BCLK
WM8731
MBIAS
VMID
AGND
AVDD
ROUT
LOUT
HPGND
21
20
19
18
17
16
15
C41 10u
A_VCC33
AGND
R104
AGND
680
C42
1n
AGND
R105
47K
AGND
AGND
J12 LINE OUT
PHONE JACK G
AUD_XCK
AUD_BCLK
AUD_DACDAT
AGND
C43
100u
AUD_DACLRCK
AUD_ADCD AT
AUD_ADCLRCK
C44
100u
A_VCC33
R106
R107
AGND
47K
AGND
47K
AGND
Figure 5.14. Audio CODEC schematic.
Signal Name
AUD_ADCLRCK
AUD_ADCDAT
AUD_DACLRCK
AUD_DACDAT
AUD_XCK
AUD_BCLK
I2C_SCLK
I2C_SDAT
FPGA Pin No.
PIN_F19
PIN_E19
PIN_G18
PIN_F18
PIN_D17
PIN_E17
PIN_J18
PIN_H18
Description
Audio CODEC ADC LR Clock
Audio CODEC ADC Data
Audio CODEC DAC LR Clock
Audio CODEC DAC Data
Audio CODEC Chip Clock
Audio CODEC Bit-Stream Clock
I2C Data
I2C Clock
Table 5.12. Audio CODEC pin assignments.
48
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